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2.7 v to 5.5 v, 450 a, rail-to-rail output, quad, 12-/16-bit nano dacs ? AD5624/ad5664 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features low power, quad nano dacs ad5664: 16 bits AD5624: 12 bits relative accuracy: 12 lsbs max guaranteed monotonic by design 10-lead msop and 3 mm 3 mm lfcsp_wd 2.7 v to 5.5 v power supply power-on reset to zero per channel power-down serial interface, up to 50 mhz applications process control data acquisition systems portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators functional block diagram interface logic sclk sync din input register dac register v dd gnd power-on reset string dac a buffer v ref v out a input register dac register string dac b buffer v out b input register dac register string dac c buffer v out c input register dac register string dac d buffer v out d AD5624/ad5664 power-down logic 05943-001 figure 1. table 1. related devices part no. description AD5624r / ad5644r / ad5664r 2.7 v to 5.5 v quad, 12-, 14-, 16-bit dacs with internal reference general description the AD5624/ad5664, members of the nano dac family, are low power, quad, 12-, 16-bit buffered voltage-out dacs that operate from a single 2.7 v to 5.5 v supply and are guaranteed monotonic by design. the AD5624/ad5664 require an external reference voltage to set the output range of the dac. the part incorporates a power- on reset circuit that ensures the dac output powers up to 0 v and remains there until a valid write takes place. the parts contain a power-down feature that reduces the current consumption of the device to 480 na at 5 v and provides software-selectable output loads while in power-down mode. the low power consumption of these parts in normal operation makes them ideally suited to portable battery-operated equipment. the power consumption is 2.25 mw at 5 v, going down to 2.4 w in power-down mode. the AD5624/ad5664 on-chip precision output amplifier allows rail-to-rail output swing to be achieved. the AD5624/ad5664 use a versatile 3-wire serial interface that operates at clock rates up to 50 mhz, and are compatible with standard spi?, qspi?, microwire?, and dsp interface standards. product highlights 1. relative accuracy: 12 lsbs maximum. 2. available in 10-lead msop and 10-lead, 3 mm 3 mm, lfcsp_wd. 3. low power, typically consumes 1.32 mw at 3 v and 2.25 mw at 5 v. 4. maximum settling time of 4.5 s (AD5624) and 7 s (ad5664).
AD5624/ad5664 rev. 0 | page 2 of 24 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 specifications..................................................................................... 3 ac characteristics........................................................................ 4 timing characteristics ................................................................ 5 timing diagram ........................................................................... 5 absolute maximum ratings............................................................ 6 esd caution.................................................................................. 6 pin configuration and function descriptions............................. 7 typical performance characteristics ............................................. 8 terminology .................................................................................... 13 theory of operation ...................................................................... 15 d/a section................................................................................. 15 resistor string ............................................................................. 15 output amplifier........................................................................ 15 serial interface ............................................................................ 15 input shift register .................................................................... 16 sync interrupt .......................................................................... 16 power-on reset.......................................................................... 16 software reset............................................................................. 17 power-down modes .................................................................. 17 ldac function .......................................................................... 18 microprocessor interfacing....................................................... 19 applications..................................................................................... 20 choosing a reference for the AD5624/ad5664.................... 20 using a reference as a power supply for the AD5624/ad5664........................................................................ 20 bipolar operation using the AD5624/ad5664..................... 21 using AD5624/ad5664 with a galvanically isolated interface ....................................................................................... 21 power supply bypassing and grounding................................ 21 outline dimensions ....................................................................... 22 ordering guide .......................................................................... 22 revision history 6 /06revision 0: initial version
AD5624/ad5664 rev. 0 | page 3 of 24 specifications v dd = +2.7 v to +5.5 v; r l = 2 k to gnd; c l = 200 pf to gnd; v ref = v dd ; all specifications t min to t max , unless otherwise noted. table 2. a grade 1 b grade 1 parameter min typ max min typ max unit conditions/comments static performance 2 ad5664 resolution 16 16 bits relative accuracy 8 16 6 12 lsb differential nonlinearity 1 1 lsb guaranteed monotonic by design AD5624 resolution 12 bits relative accuracy 0.5 1 lsb differential nonlinearity 0.25 lsb guaranteed monotonic by design zero-code error 2 10 2 10 mv all zeroes loaded to dac register offset error 1 10 1 10 mv full-scale error ?0.1 1 ?0.1 1 % of fsr all ones loaded to dac register gain error 1.5 1.5 % of fsr zero-code error drift 2 2 v/c gain temperature coefficient 2.5 2.5 ppm of fsr/c dc power supply rejection ratio ?100 ?100 db dac code = midscale ; v dd 10% dc crosstalk 10 10 v due to full-scale output change r l = 2 k to gnd or v dd 10 10 v/ma due to load current change 5 5 v due to powering down (per channel) output characteristics 3 output voltage range 0 v dd 0 v dd v capacitive load stability 2 2 nf r l = 10 10 nf r l = 2 k dc output impedance 0.5 0.5 short-circuit current 30 30 ma v dd = 5 v power-up time 4 4 s coming out of power-down mode; v dd = 5 v reference inputs reference current 170 200 170 200 a v ref = v dd = 5.5 v reference input range 0.75 v dd 0.75 v dd v reference input impedance 26 26 k logic inputs 3 input current 2 2 a all digital inputs v inl , input low voltage 0.8 0.8 v v dd = 5 v, 3 v v inh , input high voltage 2 2 v v dd = 5 v, 3 v pin capacitance 3 3 pf
AD5624/ad5664 rev. 0 | page 4 of 24 a grade 1 b grade 1 parameter min typ max min typ max unit conditions/comments power requirements v dd 2.7 5.5 2.7 5.5 v i dd (normal mode) 4 v ih = v dd , v il = gnd v dd = 4.5 v to 5.5 v 0.45 0.9 0.45 0.9 ma v dd = 2.7 v to 3.6 v 0.44 0.85 0.44 0.85 ma i dd (all power-down modes) 5 v ih = v dd , v il = gnd v dd = 4.5 v to 5.5 v 0.48 1 0.48 1 a v dd = 2.7 v to 3.6 v 0.2 1 0.2 1 a 1 temperature range: a grade an d b grade: ?40 c to +105c. 2 linearity calculated using a reduced code range: ad5664 (cod e 512 to code 65,024); AD5624 (code 32 to code 4064); output unloa ded. 3 guaranteed by design and characterization, not production tested. 4 interface inactive. all dacs active. dac outputs unloaded. 5 all dacs powered down. ac characteristics v dd = 2.7 v to 5.5 v; r l = 2 k to gnd; c l = 200 pf to gnd; v ref = v dd ; all specifications t min to t max , unless otherwise noted. 1 table 3. parameter 2 , 3 min typ max unit conditions/comments output voltage settling time ad5664 4 7 s ? to ? scale settling to 2 lsb AD5624 3 4.5 s ? to ? scale settling to 0.5 lsb slew rate 1.8 v/s digital-to-analog glitch impulse 10 nv-s 1 lsb change around major carry digital feedthrough 0.1 nv-s reference feedthrough ?90 dbs v ref = 2 v 0.1 v p-p, frequency 10 hz to 20 mhz digital crosstalk 0.1 nv-s analog crosstalk 1 nv-s dac-to-dac crosstalk 1 nv-s multiplying bandwidth 340 khz v ref = 2 v 0.1 v p-p total harmonic distortion ?80 db v ref = 2 v 0.1 v p-p, frequency = 10 khz output noise spectral density 120 nv/hz dac code = midscale, 1 khz 100 nv/hz dac code = midscale, 10 khz output noise 15 v p-p 0.1 hz to 10 hz 1 guaranteed by design and characterization, not production tested. 2 temperature range: ?40c to +105c; typical at 25c. 3 see the terminology section.
AD5624/ad5664 rev. 0 | page 5 of 24 timing characteristics all input signals are specified with t r = t f = 1 ns/v (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2 (see figure 2 ). v dd = 2.7 v to 5.5 v; all specifications t min to t max , unless otherwise noted. table 4. limit at t min , t max parameter 1 v dd = 2.7 v to 5.5 v unit conditions/comments t 1 2 20 ns min sclk cycle time t 2 9 ns min sclk high time t 3 9 ns min sclk low time t 4 13 ns min sync to sclk falling edge setup time t 5 5 ns min data setup time t 6 5 ns min data hold time t 7 0 ns min sclk falling edge to sync rising edge t 8 15 ns min minimum sync high time t 9 13 ns min sync rising edge to sclk fall ignore t 10 0 ns min sclk falling edge to sync fall ignore 1 guaranteed by design and characterization, not production tested. 2 maximum sclk frequency is 50 mhz at v dd = 2.7 v to 5.5 v. timing diagram db0 db23 t 10 sclk sync din t 1 t 9 t 7 t 2 t 3 t 6 t 5 t 4 t 8 05943-002 figure 2. serial write operation
AD5624/ad5664 rev. 0 | page 6 of 24 absolute maximum ratings t a = 25c, unless otherwise noted. table 5. parameter rating v dd to gnd ?0.3 v to +7 v v out to gnd ?0.3 v to v dd + 0.3 v v ref to gnd ?0.3 v to v dd + 0.3 v digital input voltage to gnd ?0.3 v to v dd + 0.3 v operating temperature range industrial (a grade, b grade) ?40c to +105c storage temperature range ?65c to +150c junction temperature (t j max) 150c power dissipation (t j max ? t a )/ ja lfcsp_wd package (4-layer board) ja thermal impedance 61c/w msop package (4-layer board) ja thermal impedance 142c/w jc thermal impedance 43.7c/w reflow soldering peak temperature pb-free 260c 5c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd pr ecautions are recommended to avoid performance degradation or loss of functionality.
AD5624/ad5664 rev. 0 | page 7 of 24 pin configuration and fu nction descriptions 1 v out a 10 v ref 2 v out b 9 v dd 3 gnd 8 din 4 v out c 7 sclk 5 v out d 6 sync AD5624/ ad5664 top view (not to scale) 0 5943-003 figure 3. pin configuration table 6. pin function descriptions pin no. mnemonic description 1 v out a analog output voltage from dac a. the outp ut amplifier has rail-to-rail operation. 2 v out b analog output voltage from dac b. the outp ut amplifier has rail-to-rail operation. 3 gnd ground reference point for all circuitry on the part. 4 v out c analog output voltage from dac c. the outp ut amplifier has rail-to-rail operation. 5 v out d analog output voltage from dac d. the outp ut amplifier has rail-to-rail operation. 6 sync active low control input. this is the frame sy nchronization signal for the input data. when sync goes low, it powers on the sclk and din buffers and enables the input shif t register. data is transferred in on the falling edges of the next 24 clocks. if sync is taken high before the 24 th falling edge, the rising edge of sync acts as an interrupt and the write sequence is ignored by the device. 7 sclk serial clock input. data is clocked into the input shift register on the falling ed ge of the serial clock input. data can be transferred at rates up to 50 mhz. 8 din serial data input. this device has a 24-bit input shift register . data is clocked into the register on the falling edge of the serial clock input. 9 v dd power supply input. these parts can be operated from 2.7 v to 5.5 v. the supply should be decoupled with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 10 v ref reference voltage input.
AD5624/ad5664 rev. 0 | page 8 of 24 typical performance characteristics code inl error (lsb) 10 4 6 8 0 2 ?6 ?10 ?8 ?2 ?4 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k 05943-004 v dd = v ref = 5v t a = 25c figure 4. inl ad5664 code inl error (lsb) 1.0 ?1.0 0 500 1000 1500 2000 2500 3000 3500 4000 05943-005 ?0.8 ?0.6 ?0.4 0 0.4 0.2 ?0.2 0.6 0.8 v dd = v ref = 5v t a = 25c figure 5. inl AD5624 code dnl error (lsb) 1.0 0.6 0.4 0.2 0.8 0 ?0.4 ?0.2 ?0.6 ?1.0 ?0.8 0 10k 20k 30k 40k 50k 60k 05943-006 v dd = v ref = 5v t a = 25c figure 6. dnl ad5664 dnl error (lsb) 0.20 0.10 0.05 0.15 0 ?0.05 ?0.10 ?0.20 ?0.15 05943-007 code 0 500 1000 1500 2000 2500 3000 3500 4000 v dd = v ref = 5v t a = 25c figure 7. dnl AD5624 temperature (c) error (lsb) 8 6 4 2 ?6 ?4 ?2 0 ?8 ?40 ?20 40 200 100 80 60 05856-022 min dnl max dnl max inl min inl v dd = v ref = 5v figure 8. inl error and dnl error vs. temperature v ref (v) error (lsb) 10 4 6 8 2 0 ?8 ?6 ?4 ?2 ?10 0.75 1.25 1.75 2.25 4.25 3.75 3.25 2.75 4.75 05943-009 min dnl max dnl max inl min inl v dd = 5v t a = 25c figure 9. inl and dnl error vs. v ref
AD5624/ad5664 rev. 0 | page 9 of 24 v dd (v) error (lsb) 8 6 4 2 ?6 ?4 ?2 0 ?8 2.7 3.2 3.7 4.7 4.2 5.2 05943-010 min dnl max dnl max inl min inl t a = 25c figure 10. inl and dnl error vs. supply temperature (c) error (% fsr) 0 ?0.04 ?0.02 ?0.06 ?0.08 ?0.10 ?0.18 ?0.16 ?0.14 ?0.12 ?0.20 ?40 ?20 40 200 100 80 60 05943-011 v dd = 5v gain error full-scale error figure 11. gain error and full-scale error vs. temperature temperature (c) error (mv) 1.5 1.0 0.5 0 ?2.0 ?1.5 ?1.0 ?0.5 ?2.5 ?40 ?20 40 20 08 60 100 05943-012 0 offset error zero-scale error figure 12. zero-scale error and offset error vs. temperature v dd (v) error (% fsr) 1.0 ?1.5 ?1.0 ?0.5 0 0.5 ?2.0 2.7 3.2 3.7 4.7 4.2 5.2 05943-013 gain error full-scale error figure 13. gain error and full-scale error vs. supply v dd (v) error (mv) 1.0 0.5 0 ?2.0 ?1.5 ?1.0 ?0.5 ?2.5 2.7 3.2 4.2 3.7 5.2 4.7 05943-014 zero-scale error offset error t a = 25c figure 14. zero-scale error and offset error vs. supply i dd (ma) frequen c y 0 1 2 3 4 5 6 0.41 0.42 0.43 0.44 0.45 05943-017 v dd = 5.5v t a = 25c figure 15. i dd histogram with v dd = 5.5 v
AD5624/ad5664 rev. 0 | page 10 of 24 i dd (ma) frequency 0 1 2 3 5 4 6 8 7 0.39 0.40 0.41 0.42 0.43 05943-018 v dd = 3.6v t a = 25c figure 16. i dd histogram with v dd = 3.6 v i (ma) error voltage (v) 0.20 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 ?5 ?4 ?3 ?2 ?1 0 1 2 4 35 05943-016 v dd = v ref = 5v, 3v t a = 25c dac loaded with zero scale ? sinking current dac loaded with full scale ? sourcing current figure 17. headroom at rails vs. source and sink current temperature (c) i dd (ma) 0.50 0.05 0.10 0.15 0.20 0.35 0.40 0.25 0.30 0.45 0 ?40 ?20 0 20 40 60 80 100 05943-026 t a = 25c v dd = v refin = 5v v dd = v refin = 3v figure 18. supply current vs. temperature 05943-021 time base = 4s/div v dd = v ref = 5v t a = 25c full-scale code change 0x0000 to 0xffff output loaded with 2k ? and 200pf to gnd v out = 909mv/div 1 figure 19. full-scale settling time, 5 v 05943-022 ch1 2.0v ch2 500mv m100s 125ms/s a ch1 1.28v 8.0ns/pt v dd = v ref = 5v t a = 25c v out v dd 1 2 max(c2) 420.0mv figure 20. power-on reset to 0 v 05943-023 v dd = 5v sync slck v out 1 3 ch1 5.0v ch3 5.0v ch2 500mv m400ns a ch1 1.4v 2 figure 21. exiting po wer-down to midscale
AD5624/ad5664 rev. 0 | page 11 of 24 sample number v out (v) 2.521 2.522 2.523 2.524 2.525 2.526 2.527 2.528 2.529 2.530 2.531 2.532 2.533 2.534 2.535 2.536 2.537 2.538 0 50 100 150 350 400 200 250 300 450 512 05943-024 v dd = v ref = 5v t a = 25c 5ns/sample number glitch impulse = 9.494nv 1lsb change around midscale (0x8000 to 0x7fff) figure 22. digital-to-analog glitch impulse (negative) sample number v out (v) 2.491 2.492 2.493 2.494 2.495 2.496 2.497 2.498 0 50 100 150 350 400 200 250 300 450 512 05943-025 v dd = v ref = 5v t a = 25c 5ns/sample number analog crosstalk = 0.424nv figure 23. analog crosstalk (hz) (db) ? 20 ?50 ?80 ?30 ?40 ?60 ?70 ?90 ?100 2k 4k 6k 8k 10k 05943-027 v dd = 5v t a = 25c dac loaded with full scale v ref = 2v 0.3v p-p figure 24. total harmonic distortion capacitance (nf) time (s) 16 14 12 10 8 6 4 012 34567 9 81 05943-028 0 v ref = v dd t a = 25c v dd = 5v v dd = 3v figure 25. settling time vs. capacitive load 05943-029 1 y axis = 2v/div x axis = 4s/div v dd = v ref = 5v t a = 25c dac loaded with midscale figure 26. 0.1 hz to 10 hz output noise plot frequency (hz) output noise (nv/ hz) 800 600 700 400 500 100 200 300 0 10 100k 10k 1k 100 1m 05943-030 v dd = v ref = 5v t a = 25c figure 27. noise spectral density
AD5624/ad5664 rev. 0 | page 12 of 24 frequency (hz) (db) 5 ?40 10k 100k 1m 10m 05943-031 ? 35 ? 30 ? 25 ? 20 ? 15 ? 10 ? 5 0 v dd = 5v t a = 25c figure 28. multiplying bandwidth
AD5624/ad5664 rev. 0 | page 13 of 24 terminology relative accuracy or integral nonlinearity (inl) for the dac, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. a typical inl vs. code plot can be seen in figure 4 and figure 5 . differential nonlinearity (dnl) differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. a typical dnl vs. code plot can be seen in figure 6 and figure 7 . zero-scale error zero-scale error is a measurement of the output error when zero code (0x0000) is loaded to the dac register. ideally, the output should be 0 v. the zero-code error is always positive in the AD5624/ad5664 because the output of the dac cannot go below 0 v. it is due to a combination of the offset errors in the dac and the output amplifier. zero-code error is expressed in mv. a plot of zero-code error vs. temperature can be seen in figure 12 . full-scale error full-scale error is a measurement of the output error when full- scale code (0xffff) is loaded to the dac register. ideally, the output should be v dd ? 1 lsb. full-scale error is expressed in % of fsr. a plot of full-scale error vs. temperature can be seen in figure 11 . gain error this is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from ideal expressed as a % of fsr. zero-code error drift this is a measurement of the change in zero-code error with a change in temperature. it is expressed in v/c. gain temperature coefficient this is a measurement of the change in gain error with changes in temperature. it is expressed in ppm of fsr/c. offset error offset error is a measure of the difference between v out (actual) and v out (ideal) expressed in mv in the linear region of the transfer function. offset error is measured on the AD5624/ ad5664 with code 512 loaded in the dac register. it can be negative or positive. dc power supply rejection ratio (psrr) this indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full-scale output of the dac. it is measured in db. v ref is held at 2 v, and v dd is varied by 10%. output voltage settling time this is the amount of time it takes for the output of a dac to settle to a specified level for a ? to ? full-scale input change and is measured from the 24 th falling edge of sclk. digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv-s, and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x7fff to 0x8000) as shown in figure 22 . digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac, but is measured when the dac output is not updated. it is specified in nv-s, and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. total harmonic distortion (thd) this is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac, and the thd is a measurement of the harmonics present on the dac output. it is measured in db. noise spectral density this is a measurement of the internally generated random noise. random noise is characterized as a spectral density (nv/hz). it is measured by loading the dac to midscale and measuring noise at the output. it is measured in nv/hz. a plot of noise spectral density can be seen in figure 27 . dc crosstalk dc crosstalk is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full-scale output change on one dac (or soft power-down and power-up) while monitoring another dac kept at midscale. it is expressed in v. dc crosstalk due to load current change is a measure of the impact that a change in load current on one dac has to another dac kept at midscale. it is expressed in v/ma.
AD5624/ad5664 rev. 0 | page 14 of 24 digital crosstalk this is the glitch impulse transferred to the output of one dac at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another dac. it is measured in standalone mode and is expressed in nv-s. analog crosstalk this is the glitch impulse transferred to the output of one dac due to a change in the output of another dac. it is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa). then execute a software ldac and monitor the output of the dac whose digital code was not changed. the area of the glitch is expressed in nv-s (see figure 23 ). dac-to-dac crosstalk this is the glitch impulse transferred to the output of one dac due to a digital code change and subsequent analog output change of another dac. it is measured by loading the attack channel with a full-scale code change (all 0s to all 1s and vice versa) using the command write to and update while monitoring the output of the victim channel that is at midscale. the energy of the glitch is expressed in nv-s. multiplying bandwidth the amplifiers within the dac have a finite bandwidth. the multiplying bandwidth is a measure of this. a sine wave on the reference (with full-scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequency at which the output amplitude falls to 3 db below the input.
AD5624/ad5664 rev. 0 | page 15 of 24 theory of operation d/a section the AD5624/ad5664 dacs are fabricated on a cmos process. the architecture consists of a string dac followed by an output buffer amplifier. figure 29 shows a block diagram of the dac architecture. dac register resistor string ref (+) v dd gnd ref (?) v out output amplifier (gain = +2) 05943-032 figure 29. dac architecture since the input coding to the dac is straight binary, the ideal output voltage is given by ? ? ? ? ? ? = n refin out d vv 2 where: d is the decimal equivalent of the binary code that is loaded to the dac register: 0 to 4095 for AD5624 (12 bit). 0 to 65535 for ad5664 (16 bit). n is the dac resolution. resistor string the resistor string is shown in figure 30 . it is simply a string of resistors, each of value r. the code loaded to the dac register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaranteed monotonic. output amplifier the output buffer amplifier can generate rail-to-rail voltages on its output, which gives an output range of 0 v to v dd . it can drive a load of 2 k in parallel with 1000 pf to gnd. the source and sink capabilities of the output amplifier can be seen in figure 17 . the slew rate is 1.8 v/s with a ? to ? full-scale settling time of 7 s. r r r r r to output amplifier 0 5943-033 figure 30. resistor string serial interface the AD5624/ad5664 have a 3-wire serial interface ( sync , sclk, and din) that is compatible with spi, qspi, and microwire interface standards as well as with most dsps. see figure 2 for a timing diagram of a typical write sequence. the write sequence begins by bringing the sync line low. data from the din line is clocked into the 24-bit shift register on the falling edge of sclk. the serial clock frequency can be as high as 50 mhz, making the AD5624/ad5664 compatible with high speed dsps. on the 24 th falling clock edge, the last data bit is clocked in and the programmed function is executed, that is, a change in dac register contents and/or a change in the mode of operation. at this stage, the sync line can be kept low or be brought high. in either case, it must be brought high for a minimum of 15 ns before the next write sequence so that a falling edge of sync can initiate the next write sequence. since the sync buffer draws more current when v in = 2.0 v than it does when v in = 0.8 v, sync should be idled low between write sequences for even lower power operation. it must, however, be brought high again just before the next write sequence.
AD5624/ad5664 rev. 0 | page 16 of 24 input shift register the input shift register is 24 bits wide the first two bits are dont care bits. the next three bits are the command bits, c2 to c0 (see tabl e 7 ), followed by the 3-bit dac address, a2 to a0 (see table 8 ), and then the 16-, 12-bit data-word. the data-word comprises the 16-, 12- bit input code followed by 0 or 4 dont care bits for the ad5664 and AD5624 respectively (see figure 31 and figure 32 ). these data bits are transferred to the dac register on the 24 th falling edge of sclk. table 7. command definition c2 c1 c0 command 0 0 0 write to input register n 0 0 1 update dac register n 0 1 0 write to input register n , update all (software ldac) 0 1 1 write to and update dac channel n 1 0 0 power down dac (power-up) 1 0 1 reset 1 1 0 load ldac register 1 1 1 reserved table 8. address command a2 a1 a0 address ( n ) 0 0 0 dac a 0 0 1 dac b 0 1 0 dac c 0 1 1 dac d 1 1 1 all dacs sync interrupt in a normal write sequence, the sync line is kept low for at least 24 falling edges of sclk, and the dac is updated on the 24 th falling edge. however, if sync is brought high before the 24 th falling edge, then this acts as an interrupt to the write sequence. the input shift register is reset and the write sequence is seen as invalid. neither an update of the dac register contents nor a change in the operating mode occurs (see figure 33 ). power-on reset the AD5624/ad5664 family contains a power-on reset circuit that controls the output voltage during power-up. the AD5624/ ad5664 dac outputs power up to 0 v and the output remains there until a valid write sequence is made to the dac. this is useful in applications where it is important to know the state of the output of the dac while it is in the process of powering up. x x c2 c1 c0 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 db23 (msb) db0 (lsb) command bits address bits data bits 05943-034 figure 31. ad5664 input shift register contents x x c2 c1 c0 a2 a1 a0 xxxx d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 db23 (msb) db0 (lsb) command bits address bits data bits 05943-035 figure 32. AD5624 input shift register contents din db23 db23 db0 db0 valid write sequence, output updates on the 24 th falling edge s ync sclk invalid write sequence: sync high before 24 th falling edge 05943-036 figure 33. sync interrupt facility
AD5624/ad5664 rev. 0 | page 17 of 24 software reset the AD5624/ad5664 contain a software reset function. command 110 is reserved for the software reset function (see table 7 ). the software reset command contains two reset modes that are software programmable by setting bit db0 in the control register. table 9 shows how the state of the bit corresponds to the software reset modes of operation of the devices. table 9. software reset modes for the AD5624/ad5664 db0 registers reset to zero 0 dac register input shift register 1 (power-on reset) dac register input shift register ldac register power-down register power-down modes the AD5624/ad5664 contain four se parate modes of operation. command 100 is reserved for the power-down function (see table 7 ). these modes are software programmable by setting two bits (db5 and db4) in the control register. table 10 shows how the state of the bits corresponds to the mode of operation of the device. all dacs (dac d to dac a) can be powered down to the selected mode by setting the corresponding four bits (db3, db2, db1, and db0) to 1. by executing the same command 100, any combination of dacs is powered up by setting bit db5 and bit db4 to normal operation mode. to select which combination of dac channels to power-up, set the corresponding four bits (db3, db2, db1, and db0) to 1. see table 11 for contents of the input shift register during the power-down/power-up operation. table 10. modes of operation for the AD5624/ad5664 db5 db4 operating mode 0 0 normal operation power-down modes 0 1 1 k to gnd 1 0 100 k to gnd 1 1 three-state when both bits are set to 0, the parts work normally with their normal power consumption of 450 a at 5 v. however, for the three power-down modes, the supply current falls to 480 na at 5 v (200 na at 3 v). not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. this allows the output impedance of the part to be known while the part is in power-down mode. the outputs can either be connected internally to gnd through a 1 k or 100 k resistor, or left open-circuited (three-state) (see figure 34 ). resistor network v out resistor string dac power-down circuitry amplifier 05943-037 figure 34. output stage during power-down the bias generator, the output amplifier, the resistor string, and other associated linear circuitry are shut down when power- down mode is activated. however, the contents of the dac register are unaffected when in power-down. the time to exit power-down is typically 4 s for v dd = 5 v and for v dd = 3 v (see figure 21 ). table 11. 24-bit input shift register co ntents of power-down/power-up operation db23 to db22 (msb) db21 db20 db19 db18 db17 db16 db15 to db6 db5 db4 db3 db2 db1 db0 (lsb) x 1 0 0 x x x x pd1 pd0 dac d dac c dac b dac a dont care command bits (c2 to c0) address bits (a2 to a0); dont care dont care power- down mode power-down/power-up channel selection, set bit to 1 to select channel
AD5624/ad5664 rev. 0 | page 18 of 24 ldac function the AD5624/ad5664 dacs have double-buffered interfaces consisting of two banks of regi sters: input registers and dac registers. the input registers are connected directly to the input shift register and the digital code is transferred to the relevant input register on completion of a valid write sequence. the dac registers contain the digital code used by the resistor strings. the double-buffered interface is useful if the user requires simultaneous updating of all da c outputs. the user can write to three of the input registers individually and then write to the remaining input register and update all dac registers, the outputs update simultaneously. command 010 is reserved for this software ldac. access to the dac registers is controlled by the ldac function. the ldac registers contain two modes of operation for each dac channel. the dac channels are selected by setting the bits of the 4-bit ldac register (db3, db2, db1, and db0). command 110 is reserved for setting up the ldac register. when the ldac bit register is set low, the corresponding dac registers are latched and the input registers can change state without affecting the contents of the dac registers. when the ldac bit register is set high, however, the dac registers become transparent and the contents of the input registers are transferred to them on the falling edge of the 24 th sclk pulse. this is equivalent to having an ldac hardware pin tied permanently low for the selected dac channel, that is, synchronous update mode. see table 12 for the ldac register mode of operation. see table 13 for contents of the input shift register during the ldac register set- up command. this flexibility is useful in applications where the user wants to update select channels simultaneously, while the rest of the channels update synchronously. table 12. ldac register mode of operation load dac register ldac bits (db3 to db0) ldac mode of operation 0 normal operation (default), dac register update is controlled by write command. 1 the dac registers are updated after new data is read in on the falling edge of the 24 th sclk pulse. table 13. 24-bit input shift register contents for ldac setup command for the AD5624/ad5664 db23 to db22 (msb) db21 db20 db19 db18 db17 db16 db15 to db4 db3 db2 db1 db0 (lsb) x 1 1 0 x x x x dacd dacc dacb daca dont care command bits (c2 to c0) address bits (a3 to a0); dont care dont cares set bit to 0 or 1 for required mode of operation on respective channel
AD5624/ad5664 rev. 0 | page 19 of 24 microprocessor interfacing AD5624/ad5664 to black fin? adsp-bf53x interface figure 35 shows a serial interface between the AD5624/ad5664 and the black fin adsp-bf53x microprocessor. the adsp-bf53x processor family incorporates two dual-channel synchronous serial ports, sport1 and sport0, for serial and multiprocessor commu- nications. using sport0 to connect to the AD5624/ad5664, the setup for the interface is as follows. dtopri drives the din pin of the AD5624/ad5664, while tsclk0 drives the sclk of the part. the sync is driven from tfs0. AD5624/ ad5664 1 adsp-bf53x 1 sync tfs0 din dtopri sclk tsclk0 1 additional pins omitted for clarity. 05943-038 figure 35. black fin adsp-bf53x interface to AD5624/ad5664 AD5624/ad5664 to 68hc11/68l11 interface figure 36 shows a serial interface between the AD5624/ad5664 and the 68hc11/68l11 microcontroller. sck of the 68hc11/ 68l11 drives the sclk of the AD5624/ad5664, while the mosi output drives the serial data line of the dac. the sync signal is derived from a port line (pc7). the setup conditions for correct operation of this interface are as follows. the 68hc11/68l11 is configured with its cpol bit as a 0 and its cpha bit as a 1. when data is being transmitted to the dac, the sync line is taken low (pc7). when the 68hc11/68l11 is configured as described previously, data appearing on the mosi output is valid on the falling edge of sck. serial data from the 68hc11/68l11 is transmitted in 10-bit bytes with only eight falling clock edges occurring in the transmit cycle. data is transmitted msb first. to load data to the AD5624/ad5664, pc7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the dac; pc7 is taken high at the end of this procedure. AD5624/ ad5664 1 68hc11/68l11 1 sync pc7 sclk sck din mosi 1 additional pins omitted for clarity. 05943-039 figure 36. 68hc11/68l11 interface to AD5624/ad5664 AD5624/ad5664 to 80c51/80l51 interface figure 37 shows a serial interface between the AD5624/ad5664 and the 80c51/80l51 microcontroller. the setup for the interface is as follows. txd of the 80c51/80l51 drives sclk of the AD5624/ad5664, while rxd drives the serial data line of the part. the sync signal is derived from a bit-programmable pin on the port. in this case, port line p3.3 is used. when data is transmitted to the AD5624/ad5664, p3.3 is taken low. the 80c51/80l51 transmits data in 10-bit bytes only; thus only eight falling clock edges occur in the transmit cycle. to load data to the dac, p3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. p3.3 is taken high following the completion of this cycle. the 80c51/80l51 output the serial data in a format that has the lsb first. the AD5624/ad5664 must receive data with the msb first. the 80c51/80l51 transmit routine should take this into account. AD5624/ ad5664 1 80c51/80l51 1 sync p3.3 sclk txd din rxd 1 additional pins omitted for clarity. 05943-040 figure 37. 80c51/80l51 interface to AD5624/ad5664 AD5624/ad5664 to microwire interface figure 38 shows an interface between the AD5624/ad5664 and any microwire-compatible device. serial data is shifted out on the falling edge of the serial clock and is clocked into the AD5624/ad5664 on the rising edge of the sk. AD5624/ ad5664 1 microwire 1 sync cs sclk sk din so 1 additional pins omitted for clarity. 05943-041 figure 38. microwire interface to AD5624/ad5664
AD5624/ad5664 rev. 0 | page 20 of 24 applications choosing a reference for the AD5624/ad5664 to achieve the optimum performance from the AD5624/ ad5664, thought should be given to the choice of a precision voltage reference. the AD5624/ad5664 have only one reference input, v ref . the voltage on the reference input is used to supply the positive input to the dac. therefore, any error in the reference is reflected in the dac. when choosing a voltage reference for high accuracy applica- tions, the sources of error are initial accuracy, ppm drift, long- term drift, and output voltage noise. initial accuracy on the output voltage of the dac leads to a full-scale error in the dac. to minimize these errors, a reference with high initial accuracy is preferred. choosing a reference with an output trim adjustment, such as the adr423 , allows a system designer to trim out system errors by setting a reference voltage to a voltage other than the nominal. the trim adjustment can also be used at temperature to trim out any error. long-term drift is a measurement of how much the reference drifts over time. a reference with a tight long-term drift specification ensures that the overall solution remains relatively stable during its entire lifetime. the temperature coefficient of a references output voltage affects inl, dnl, and tue. a reference with a tight temperature coefficient specification should be chosen to reduce temperature dependence of the dac output voltage in ambient conditions. in high accuracy applications, which have a relatively low noise budget, reference output voltage noise needs to be considered. it is important to choose a reference with as low an output noise voltage as practical for the system noise resolution required. precision voltage references such as the adr425 produce low output noise in the 0.1 hz to10 hz range. examples of recom- mended precision references for use as supply to the AD5624/ad5664 are shown in the table 14 . using a reference as a power supply for the AD5624/ad5664 because the supply current required by the AD5624/ad5664 is extremely low, an alternative option is to use a voltage reference to supply the required voltage to the part (see figure 39 ). this is especially useful if the power supply is quite noisy, or if the system supply voltages are at some value other than 5 v or 3 v, for example, 15 v. the voltage reference outputs a steady supply voltage for the AD5624/ad5664 (see table 14 for a suitable reference). if the low dropout ref195 is used, it must supply 450 a of current to the AD5624/ad5664, with no load on the output of the dac. when the dac output is loaded, the ref195 also needs to supply the current to the load. the total current required (with a 5 k load on the dac output) is 450 a + (5 v/5 k) = 1.45 ma the load regulation of the ref195 is typically 2 ppm/ma, which results in a 2.9 ppm (14.5 v) error for the 1.45 ma current drawn from it. this corresponds to a 0.191 lsb error. AD5624/ ad5664 3-wire serial interface sync sclk din 15 v 5v 500ma v out = 0v to 5v v dd ref195 v ref 05943-042 figure 39. ref195 as power supply to the AD5624/ad5664 table 14. partial list of precision re ferences for use with the AD5624/ad5664 part no. initial accuracy (mv max) temp drift (ppm o c max) 0.1 hz to 10 hz noise (v p-p typ) v out (v) adr425 2 3 3.4 5 adr395 6 25 5 5 ref195 2 5 50 5 ad780 2 3 4 2.5/3 adr423 2 3 3.4 3
AD5624/ad5664 rev. 0 | page 21 of 24 bipolar operation using the AD5624/ad5664 the AD5624/ad5664 have been designed for single-supply operation, but a bipolar output range is also possible using the circuit in figure 40 . the circuit gives an output voltage range of 5 v. rail-to-rail operation at the amplifier output is achievable using an ad820 or an op295 as the output amplifier. the output voltage for any input code can be calculated as follows: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? = r1 r2 v r1 r2r1d vv dd dd o 536,65 where d represents the input code in decimal (0 to 65536). with v dd = 5 v, r1 = r2 = 10 k, v5 536,65 10 ? ? ? ? ? ? ? = d v o this is an output voltage range of 5 v, with 0x0000 corre- sponding to a ?5 v output, and 0xffff corresponding to a +5 v output. 3-wire serial interface r2 = 10k ? +5v ?5v ad820/ op295 +5v AD5624/ ad5664 v dd v out r1 = 10k ? 5v 0.1f 10f 05943-043 figure 40. bipolar operation with the AD5624/ad5664 using AD5624/ad5664 with a galvanically isolated interface in process control applications in industrial environments, it is often necessary to use a galvanically isolated interface to protect and isolate the controlling circuitry from any hazardous common-mode voltages that might occur in the area where the dac is functioning. isocouplers provide isolation in excess of 3 kv. the AD5624/ad5664 use a 3-wire serial logic interface, so the adum130x 3-channel digital isolator provides the required isolation (see figure 41 ). the power supply to the part also needs to be isolated, which is done by using a transformer. on the dac side of the transformer, a 5 v regulator provides the 5 v supply required for the AD5624/ad5664. 0.1f 5v regulator gnd din sync sclk power 10f sdi sclk data AD5624/ ad5664 v out vob voa voc v dd v1c v1b v1a adum1300 05943-044 figure 41. AD5624/ad5664 with a galvanically isolated interface power supply bypassing and grounding when accuracy is important in a circuit, it is helpful to consider carefully the power supply and ground return layout on the board. the printed circuit board containing the AD5624/ ad5664 should have separate analog and digital sections, each having its own area of the board. if the AD5624/ad5664 is in a system where other devices require an agnd-to-dgnd connection, the connection should be made at one point only. this ground point should be as close as possible to the AD5624/ad5664. the power supply to the AD5624/ad5664 should be bypassed with 10 f and 0.1 f capacitors. the capacitors should be located as close as possible to the device, with the 0.1 f capacitor ideally right up against the device. the 10 f capacitor is the tantalum bead type. it is important that the 0.1 f capacitor has low effective series resistance (esr) and effective series inductance (esi), for example, common ceramic types of capacitors. this 0.1 f capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. the power supply line itself should have as large a trace as possible to provide a low impedance path and to reduce glitch effects on the supply line. clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. avoid crossover of digital and analog signals if possible. when traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. the best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. however, this is not always possible with a 2-layer board.
AD5624/ad5664 rev. 0 | page 22 of 24 outline dimensions 3.00 bsc sq index area top view 1.50 bcs sq exposed pad (bottom view) 1.74 1.64 1.49 2.48 2.38 2.23 1 6 10 0.50 bsc 0.50 0.40 0.30 5 pin 1 indicator 0.80 0.75 0.70 0.05 max 0.02 nom s eating plane 0.30 0.23 0.18 0.20 ref 0.80 max 0.55 typ side view figure 42. 10-lead lead frame chip scale package [lfcsp_wd] 3 mm 3 mm body, very very thin, dual lead (cp-10-9) dimensions shown in millimeters compliant to jedec standards mo-187-ba 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.05 0.33 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc pin 1 coplanarity 0.10 3.10 3.00 2.90 3.10 3.00 2.90 5.15 4.90 4.65 figure 43. 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters ordering guide model temperature range accuracy package description package option branding AD5624brmz ?40c to +105c 1 lsb inl 10-lead msop rm-10 d5j AD5624brmz-reel7 ?40c to +105c 1 lsb inl 10-lead msop rm-10 d5j AD5624bcpz-250rl7 ?40c to +105c 1 lsb inl 10-lead lfcsp_wd cp-10-9 d5j AD5624bcpz-reel7 ?40c to +105c 1 lsb inl 10-lead lfcsp_wd cp-10-9 d5j ad5664armz ?40c to +105c 16 lsb inl 10-lead msop rm-10 d7c ad5664armz-reel7 ?40c to +105c 16 lsb inl 10-lead msop rm-10 d7c ad5664brmz ?40c to +105c 12 lsb inl 10-lead msop rm-10 d78 ad5664brmz-reel7 ?40c to +105c 12 lsb inl 10-lead msop rm-10 d78 ad5664bcpz-250rl7 ?40c to +105c 12 lsb inl 10-lead lfcsp_wd cp-10-9 d78 ad5664bcpz-reel7 ?40c to +105c 12 lsb inl 10-lead lfcsp_wd cp-10-9 d78
AD5624/ad5664 rev. 0 | page 23 of 24 notes
AD5624/ad5664 rev. 0 | page 24 of 24 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05943-0- 6/06(0)

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